AVR processor registers for Arduino

published: 21 April 2020 / updated 2 October 2020

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Data Ports

Each port is controlled by three registers, which are also defined variables in the arduino language. The DDR register, determines whether the pin is an INPUT or OUTPUT. The PORT register controls whether the pin is HIGH or LOW, and the PIN register reads the state of INPUT pins set to input.

DDR and PORT registers may be both written to, and read. PIN registers correspond to the state of inputs and may only be read.

All ARDUINO cards

\ PORTB 
37 constant PORTB	\ Port B Data Register 
36 constant DDRB	\ Port B Data Direction Register 
35 constant PINB	\ Port B Input Pins 
\ PORTC 
40 constant PORTC	\ Port C Data Register 
39 constant DDRC	\ Port C Data Direction Register 
38 constant PINC	\ Port C Input Pins 
\ PORTD 
43 constant PORTD	\ Port D Data Register 
42 constant DDRD	\ Port D Data Direction Register 
41 constant PIND	\ Port D Input Pins 

ARDUINO MEGA 2560 cards

\ PORTA 
34 constant PORTA	\ Port A Data Register 
33 constant DDRA	\ Port A Data Direction Register 
32 constant PINA	\ Port A Input Pins 
\ PORTB 
37 constant PORTB	\ Port B Data Register 
36 constant DDRB	\ Port B Data Direction Register 
35 constant PINB	\ Port B Input Pins 
\ PORTC 
40 constant PORTC	\ Port C Data Register 
39 constant DDRC	\ Port C Data Direction Register 
38 constant PINC	\ Port C Input Pins 
\ PORTD 
43 constant PORTD	\ Port D Data Register 
42 constant DDRD	\ Port D Data Direction Register 
41 constant PIND	\ Port D Input Pins 
\ PORTE 
46 constant PORTE	\ Data Register, Port E 
45 constant DDRE	\ Data Direction Register, Port E 
44 constant PINE	\ Input Pins, Port E 
\ PORTF 
49 constant PORTF	\ Data Register, Port F 
48 constant DDRF	\ Data Direction Register, Port F 
47 constant PINF	\ Input Pins, Port F 
\ PORTG 
52 constant PORTG	\ Data Register, Port G 
51 constant DDRG	\ Data Direction Register, Port G 
50 constant PING	\ Input Pins, Port G 
\ PORTH 
258 constant PORTH	\ PORT H Data Register 
257 constant DDRH	\ PORT H Data Direction Register 
256 constant PINH	\ PORT H Input Pins 
\ PORTJ 
261 constant PORTJ	\ PORT J Data Register 
260 constant DDRJ	\ PORT J Data Direction Register 
259 constant PINJ	\ PORT J Input Pins 
\ PORTK 
264 constant PORTK	\ PORT K Data Register 
263 constant DDRK	\ PORT K Data Direction Register 
262 constant PINK	\ PORT K Input Pins 
\ PORTL 
267 constant PORTL	\ PORT L Data Register 
266 constant DDRL	\ PORT L Data Direction Register 
265 constant PINL	\ PORT L Input Pins 

DDRn - Data Direction Register

This register is very simple to operate and is linked to the operation of the corresponding PORT.

Each DDRn bit set to 0 configures the corresponding input pin. Each bit at 1 sets the pin out.

At startup or reset, all pins are input, so as not to send signals unwanted on pines. The bits of DDRn will therefore be set to 0 during each reset.

Example, for PORTB:

37 constant PORTB	\ Port B Data Register 
36 constant DDRB	\ Port B Data Direction Register 
%00000001   DDRB c!     \ set B0 in output mode 
%00000001   PORTB c!    \ activate B0 in high level 

PORTn

On the ARDUINO card, A port controls 8 pins. Each bit in a port selects a binary state on the corresponding terminal. Example, for PORT B:

PINn

Timer/Counter1 Control Register

128 constant TCCR1A	\ Timer/Counter1 Control Register A 
  $c0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits 
  $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits 
  $03 constant TCCR1A_WGM1 \ Waveform Generation Mode 
129 constant TCCR1B	\ Timer/Counter1 Control Register B 
  $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler 
  $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select 
  $18 constant TCCR1B_WGM1 \ Waveform Generation Mode 
  $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1 
130 constant TCCR1C	\ Timer/Counter1 Control Register C 
  $80 constant TCCR1C_FOC1A 
  $40 constant TCCR1C_FOC1B 

TCCR1A

...

COM1A1 COM1A0

Compare Output Mode bits 1/0; These bits control if and how the Compare Output pin is connected to Timer1.

WGM11/WGM10

Pulse Width Modulator select bits; These bits select if Timer1 is a PWM and it's resolution from 8 to 10 bits:

TCCR1B

ICNC1

Input Capture Noise Canceler. If set, the Noise Canceler on the ICP pin is activated. It will trigger the input capture after 4 equal samples. The edge to be triggered on is selected by the ICES1 bit.

ICES1

Input Capture Edge Select;

When cleared, the contents of TCNT1 are transferred to ICR (Input Capture Register) on the falling edge of the ICP pin.

If set, the contents of TCNT1 are transferred on the rising edge of the ICP pin.

CTC1

Clear Timer/Counter 1 on Compare Match; If set, the TCNT1 register is cleared on compare match. Use this bit to create repeated Interrupts after a certain time, e.g. to handle button debouncing or other frequently occuring events. Timer 1 is also used in normal mode, remember to clear this bit when leaving compare match mode if it was set. Otherwise the timer will never overflow and the timing is corrupted.

CS12 CS11 CS10

Clock Select bits; These three bits control the prescaler of timer/counter 1 and the connection to an external clock on Pin T1.

TCCR1C Timer/Counter1 Control Register C

Bit 7 – FOC1A:

Force Output Compare for Channel A

Bit 6 – FOC1B:

Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero.

USART0

TWI

TWCR (TWI Conrol Register)

Timer Counter 1

111 constant TIMSK1	\ Timer/Counter Interrupt Mask Register 
  $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable 
  $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable 
  $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable 
  $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable 
54 constant TIFR1	\ Timer/Counter Interrupt Flag register 
  $20 constant TIFR1_ICF1 \ Input Capture Flag 1 
  $04 constant TIFR1_OCF1B \ Output Compare Flag 1B 
  $02 constant TIFR1_OCF1A \ Output Compare Flag 1A 
  $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag 
132 constant TCNT1	\ Timer/Counter1  Bytes 
136 constant OCR1A	\ Timer/Counter1 Output Compare Register  Bytes 
138 constant OCR1B	\ Timer/Counter1 Output Compare Register  Bytes 
134 constant ICR1	\ Timer/Counter1 Input Capture Register  Bytes 
67 constant GTCCR	\ General Timer/Counter Control Register 
  $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode 
  $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0 

TIMSK1

TIFR1

TCNT1

OCR1A

Registre 16 bits.

OCR1B

Registre 16 bits.

ICR1

Registre 16 bits.

GTCCR

TIMER COUNTER 2

TCCR2A Timer/Counter2 Control Register A

TCCR2B Timer/Counter2 Control Register B

AD Converter

124 constant ADMUX	\ The ADC multiplexer Selection Register 
  $c0 constant ADMUX_REFS \ Reference Selection Bits 
  $20 constant ADMUX_ADLAR \ Left Adjust Result 
  $0f constant ADMUX_MUX \ Analog Channel and Gain Selection Bits 
120 constant ADC	\ ADC Data Register  Bytes 
122 constant ADCSRA	\ The ADC Control and Status register A 
  $80 constant ADCSRA_ADEN \ ADC Enable 
  $40 constant ADCSRA_ADSC \ ADC Start Conversion 
  $20 constant ADCSRA_ADATE \ ADC  Auto Trigger Enable 
  $10 constant ADCSRA_ADIF \ ADC Interrupt Flag 
  $08 constant ADCSRA_ADIE \ ADC Interrupt Enable 
  $07 constant ADCSRA_ADPS \ ADC  Prescaler Select Bits 
123 constant ADCSRB	\ The ADC Control and Status register B 
  $40 constant ADCSRB_ACME \ 
  $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits 
126 constant DIDR0	\ Digital Input Disable Register 
  $20 constant DIDR0_ADC5D \ 
  $10 constant DIDR0_ADC4D \ 
  $08 constant DIDR0_ADC3D \ 
  $04 constant DIDR0_ADC2D \ 
  $02 constant DIDR0_ADC1D \ 
  $01 constant DIDR0_ADC0D \ 

External Interrupts

105 constant EICRA	\ External Interrupt Control Register 
  $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits 
  $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits 
61 constant EIMSK	\ External Interrupt Mask Register 
  $03 constant EIMSK_INT \ External Interrupt Request 1 Enable 
60 constant EIFR	\ External Interrupt Flag Register 
  $03 constant EIFR_INTF \ External Interrupt Flags 
104 constant PCICR	\ Pin Change Interrupt Control Register 
  $07 constant PCICR_PCIE \ Pin Change Interrupt Enables 
109 constant PCMSK2	\ Pin Change Mask Register 2 
  $FF constant PCMSK2_PCINT \ Pin Change Enable Masks 
108 constant PCMSK1	\ Pin Change Mask Register 1 
  $7F constant PCMSK1_PCINT \ Pin Change Enable Masks 
107 constant PCMSK0	\ Pin Change Mask Register 0 
  $FF constant PCMSK0_PCINT \ Pin Change Enable Masks 
59 constant GICR	\ Pin Change Interrupt Flag Register 
  $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags 

PCICR - Pin Change Interrupt Control Register

The Pin Change Interrupts are turned on by setting certain bits in the PCICR register as seen below. Bit 0 turns on port B (PCINT0 – PCINT7), bit 1 turns on port C (PCINT8 – PCINT14), and bit 2 turns on port D (PCINT16 – PCINT23).

%00000001 PCICR c!    \ turn on port b 
%00000010 PCICR c!    \ turn on port c 
%00000100 PCICR c!    \ turn on port d 
%00000111 PCICR c!    \ turn on all ports 

PCMSK Pin Change Mask Register

GICR General Interrupt Control Register

The GICR Register is used to enable INT0 and INT1 interrupts. These interrupts correspond to the two physical pins PD3 and PD4 respectively. The INT0 is configured to produce low level triggered and INT1 as falling edge triggered interrupt respectively. A counter is increment and displayed when the interrupt occurs.

MCUCR MCU Control Register

The MCUCR register allows us to configure the type of interrupt we need.

For INT0:

Watchdog

\ WATCHDOG 
96 constant WDTCSR	\ Watchdog Timer Control Register 
  $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag 
  $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable 
  $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits 
  $10 constant WDTCSR_WDCE \ Watchdog Change Enable 
  $08 constant WDTCSR_WDE \ Watch Dog Enable 

Le chien de garde ou Watchdog, est un compteur qui permet de palier au blocage du microcontrôleur. Ce blocage peut être d’ordre logiciel (retour impossible, mis en boucle infinie ou tout simplement erreur de structuration), soit matériel (parasites, chute de tensions) ; dans les deux cas, le blocage du programme peut avoir des conséquences très embêtantes.

WDTCSR Watchdog Timer Control Register

WDIF

Sets an interrupt flag but you wont need to worry about this. It is automatically flagged high and low by the system.

WDIE

Enables Interrupts. This will give you the chance to include one last dying wish (or a few lines of code...) before the board is reset. This is a great way of performing interrupts on a regular interval should the watchdog be configured to not reset on time-out.

WDCE

This is a safety to enable a configuration mode that will last 4 clock cycles. Set this bit and WDE high before attempting any changes to the watchdog register. There isnʼt really any logic behind this, you just have to set WDCE and WDE to ʻ1ʼ to enter a sort of ʻsetup modeʼ in the watchdog timer.

WDE

Enables system reset on time-out. Whenever the Watchdog timer times out the micocontroller will be reset. This is probably what you were all looking for. Set this to ʻ1ʼ to activate.

WDP0/WDP1/WDP2/WDP3

These four bits determine how long the timer will count for before resetting. The exact time is set by setting combinations of the 4 bits in such a pattern.

MCUCR MCU Control Register